# Cisco Paper

1. On cmos power( formula- P=CV*Vf

2. Lowest noise margin in which logic family–

a) TTL b) CMOS c) biCMOS d) all have same

3. If CMOS has tr(rise time)=tf.find Wp/Wn. given beta(n)=2*beta(p)

4. gm of a [shal]transistor[/shal] is proportional to

a)Ic b)Vt c)1/Vt d)none

5. If A and B are given in 2’s complement find A-B in decimal.

6. Set up time,hold time ,clock to Q delay time (very important)

7. .3 questions on opamp (transfer function)(2 marks each)

8. 2 questions on sequence detector (2 marks each)

9. Logic function boolean expressions(true/false) (3 question-1 mark each) probably all false

10. In I/O mapped how do you represent memory(1 mark)

11. The design of FSM(finite state machine) will–

a) increase time of design

b) increase delay

c) increase power

d) all of the above

12. K-map minimization

13. Phase locked loop(PLL) 1 question sachin